module producer (clock, v_o, r_i, d_o, addrOut);
	parameter mem_depth = 32;
	parameter mem_width = 16;
	input clock;
	output reg v_o;
	input r_i;
	output [15:0] d_o;
	
	parameter addr_width = ( (((mem_depth)) ==0) ? 0 // - addr_count==0 LOG2=0
			: (((mem_depth-1)>>0)==0) ? 0 // - addr_count<=1 LOG2=0
			: (((mem_depth-1)>>1)==0) ? 1 // - addr_count<=2 LOG2=1
			: (((mem_depth-1)>>2)==0) ? 2 // - addr_count<=4 LOG2=2
			: (((mem_depth-1)>>3)==0) ? 3 // - addr_count<=8 LOG2=3
			: (((mem_depth-1)>>4)==0) ? 4 // - addr_count<=16 LOG2=4
			: (((mem_depth-1)>>5)==0) ? 5 // - addr_count<=32 LOG2=5
			: (((mem_depth-1)>>6)==0) ? 6 // - addr_count<=64 LOG2=6
			: (((mem_depth-1)>>7)==0) ? 7 // - addr_count<=128 LOG2=7
			: 8) // - addr_count<=256 LOG2=8
			;
	
	
	output [addr_width-1:0] addrOut;
	
	
	reg [addr_width-1:0] addr;
	
	reg [mem_width-1:0] mem [mem_depth-1:0];
	reg [addr_width:0] counter;
	assign addrOut = addr;

	
	
	initial begin
		// synthesis loop_limit 256
		for(counter = 0; counter < mem_depth; counter=counter+1) begin
			mem[counter] <= counter;
		end
		v_o <= 1;
		addr <= 0;
	end
	
	always @(posedge clock) begin
		addr <= (r_i & v_o) ? addr + 1 : addr;
		v_o <= ((addr == 31) && (r_i)) ? 0 : 1;
	end
	
	assign d_o = mem[addr];
	

endmodule 